The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structure.
In the past, the semiconductor industry utilized various semiconductor methods to produce complementary metal oxide semiconductor (MOS) transistors on a semiconductor die and to produce both MOS and bipolar transistors on the same semiconductor die. Isolation between two semiconductor devices generally was one of two types, junction isolation or dielectric isolation or a combination thereof. Junction isolation relied on transistor implementation such that there was always a reverse biased junction between devices which blocked unwanted current between devices. A second constraint to blocking unwanted current was that the depletion spread from one reverse biased junction could not reach any other junction's depletion region. A third constraint to blocking unwanted current was that the bipolar action of any parasitic PNP or NPN devices had to be small, in other words, immunity to latch-up was required. For example, two N-MOS devices could set in the same P-type well and be junction isolated from each other as long as the P-type well voltage was equal to or lower than the two N-type source regions and the two N-type drain regions, and the P-N junction depletion spread between two devices did not touch. A second example could have been that N-MOS and P-MOS devices were junction isolated from each other as long as the N-type well region of the P-MOS devices were at a higher voltage than the P-type well region of the N-MOS devices, and that current in the parasitic device made up of the N-MOS drain, N-MOS P-type well, and P-MOS N-type well was negligible. A third example was that bipolar devices generally needed a specific region added to ensure a reverse biased junction at all times to achieve junction isolation, that is, there needed to be another junction besides the emitter/base or base/collector junction. This junction could have been an emitter/isolation junction, base/isolation junction or a collector/isolation junction.
Implementation of junction isolated semiconductor devices was limited to thin field oxide layers with shallow diffused field implant regions for CMOS devices or deep diffused isolation areas, often called sinker regions. The shallow, typically less than one micron deep, diffused field implants did not provide adequate isolation and latch-up protection for the devices that included the MOS transistors. The sinker regions required a large mask opening for the diffusion source so that the diffusion did not become source limited. Also, the width of the doped region typically was about one hundred forty percent (140%) of the vertical diffusion. During operation, the width increased about another thirty percent so that the electrical width of the sinker region was about the same as the depth of the sinker region. Thus, the device spacings had to include extra space for the electrical depletion spread. These issues limited the integration density and scalability of the process that used the sinker regions. Additionally, since the MOS devices relied on shallow diffused field implant regions the design rules for the MOS devices had significant limitations in order to limit latch-up conditions. For example, the latch-up rules required large spacing between an N-channel source/drain diffusion and a P-channel source/drain diffusion. Thus, source and drain diffusions could not be on the edge of their respective wells. These rules were especially large for devices close to the input or output of the circuit. Such latch-up rules also limited scaling of the MOS devices and reduced integration density.
Oxide lined trench isolation was used in some bipolar applications. The oxide lined trenches provided low parasitics associated with the dielectric isolation and the smaller spacing rules. The oxide lined trenches did not significantly reduce cross-talk or ac carrier flow between the transistors. Additionally, the intrinsic bipolar device was not scalable so the use of oxide lined trenches did not result in size and cost reduction.
Accordingly, there is a need for semiconductor devices and processes therefor that provide improved latch-up protection, that provides improved isolation between transistors on a semiconductor die, that minimizes space utilization to provide high integration density.
For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. Although the devices are explained herein as certain N-channel or P-Channel devices, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with the present invention. For clarity of the drawings, doped regions of device structures are illustrated as having generally straight-line edges and precise angular corners. However, those skilled in the art understand that due to the diffusion and activation of dopants the edges of doped regions are generally not straight lines and the corners are not precise angles.